Modeling the effect of hot lots in semiconductor manufacturing systems

Author

Narahari, Y.

Author_Institution

Dept. of Comput. Sci. & Autom., Indian Inst. of Sci., Bangalore

Volume

10

Issue

1

fYear

1997

fDate

2/1/1997 12:00:00 AM

Firstpage

185

Lastpage

188

Abstract

The presence of hot lots or high-priority jobs in semiconductor manufacturing systems is known to significantly affect the cycle time and throughput of the regular lots since the hot lots get priority at all stages of processing. In this paper, we present an efficient analytical model based on re-entrant lines and use an efficient, approximate analysis methodology for this model in order to predict the performance of a semiconductor manufacturing line in the presence of hot lots. The proposed method explicitly models scheduling policies and can be used for rapid performance analysis. Using the analytical method and also simulation, we analyze two re-entrant lines, including a full-scale model of a wafer fab, under various buffer priority scheduling policies. The numerical results show the severe effects hot lots can have on the performance characteristics of regular lots

Keywords

approximation theory; integrated circuit manufacture; modelling; production control; production engineering computing; semiconductor device manufacture; analytical model; approximate analysis methodology; buffer priority scheduling policies; cycle time; high-priority jobs; hot lots; rapid performance analysis; re-entrant lines; scheduling policies; semiconductor manufacturing line performance; semiconductor manufacturing systems; throughput; wafer fab model; Analytical models; Job shop scheduling; Manufacturing systems; Performance analysis; Predictive models; Pulp manufacturing; Semiconductor device manufacture; Semiconductor device modeling; Throughput; Virtual manufacturing;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.554507

Filename

554507