• DocumentCode
    129071
  • Title

    Rewiring for threshold logic circuit minimization

  • Author

    Chia-Chun Lin ; Chun-Yao Wang ; Yung-Chih Chen ; Ching-Yi Huang

  • Author_Institution
    Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • fYear
    2014
  • fDate
    24-28 March 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Recently, many works have been focused on synthesis, verification, and testing of threshold circuits due to the rapid development in efficient implementation of threshold logic circuits. To minimize the hardware cost of threshold circuit implementation, this paper proposes a heuristic that consists of rewiring operations and a simplification procedure. Additionally, a subset of input vectors of a gate, called critical-effect vectors, are proved to be complete for formally verifying the equivalence of two threshold logic gates, instead of the whole truth table in this paper. This achievement can accelerate the equivalence checking of two threshold logic gates. The experimental results show that the proposed heuristic can efficiently reduce the cost.
  • Keywords
    circuit optimisation; logic circuits; logic design; logic gates; logic testing; minimisation; critical-effect vectors; equivalence checking; hardware cost minimization; heuristic; input vector subset; rewiring operations; threshold logic circuit minimization; threshold logic circuit synthesis; threshold logic circuit testing; threshold logic circuit verification; threshold logic gates; Computer science; Educational institutions; Logic circuits; Logic gates; Minimization; Vectors; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
  • Conference_Location
    Dresden
  • Type

    conf

  • DOI
    10.7873/DATE.2014.134
  • Filename
    6800335