A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design

Author

Eo, Yungseon ; Eisenstadt, William R. ; Jeong, Ju Young ; Kwon, Oh-Kyong

Author_Institution

Dept. of Electron. Eng., Hanyang Univ., Kyungki-do, South Korea

Volume

47

Issue

1

fYear

2000

fDate

1/1/2000 12:00:00 AM

Firstpage

129

Lastpage

140

Abstract

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design

Keywords

CMOS integrated circuits; SPICE; VLSI; circuit CAD; circuit simulation; crosstalk; high-speed integrated circuits; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; 0.35 micron; CAD analysis tools; CMOS VLSI; SPICE simulations; circuit design; closed-form crosstalk model; device nonlinearity; distributed transmission behavior; driven port; driving port; geometrical structures; high-speed ICs; interconnect capacitance; interconnect resistance; lumped configuration; multiple line crosstalk behaviors; on-chip interconnect crosstalk model; process-based interconnect test structures; signal integrity; CMOS process; Capacitance; Circuit testing; Crosstalk; Design automation; Integrated circuit interconnections; Linear approximation; Predictive models; SPICE; Semiconductor device modeling;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.817578

Filename

817578