A general approach to compact threshold voltage formulation based on 2D numerical simulation and experimental correlation for deep-submicron ULSI technology development [CMOS]

Author

Zhou, Xing ; Khee Yong Lim ; Lim, David

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore

Volume

47

Issue

1

fYear

2000

fDate

1/1/2000 12:00:00 AM

Firstpage

214

Lastpage

221

Abstract

A unified compact threshold voltage model is developed, which accounts for the normal and reverse short-channel effects with full range of body- and drain-bias conditions, and has been verified with experimental data down to 0.18 μm. The model only has five process-dependent fitting parameters with a simple one-iteration extraction procedure, and can be correlated to process variables for aiding new deep-submicron technology development. The approach to the model formulation is original and general, and can be extended to other key device performance parameters

Keywords

CMOS integrated circuits; ULSI; circuit simulation; integrated circuit modelling; iterative methods; technology CAD (electronics); 0.18 micron; 2D numerical simulation; body-bias conditions; deep-submicron ULSI technology; drain-bias conditions; model formulation; one-iteration extraction procedure; process variables; process-dependent fitting parameters; short-channel effects; threshold voltage formulation; CMOS technology; Calibration; Equations; Fitting; MOSFET circuits; Numerical simulation; Predictive models; Semiconductor device modeling; Threshold voltage; Ultra large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.817588

Filename

817588