• DocumentCode
    1292584
  • Title

    Analog floating-gate synapses for general-purpose VLSI neural computation

  • Author

    Lee, Bang W. ; Sheu, Bing J. ; Yang, Han

  • Author_Institution
    Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
  • Volume
    38
  • Issue
    6
  • fYear
    1991
  • fDate
    6/1/1991 12:00:00 AM
  • Firstpage
    654
  • Lastpage
    658
  • Abstract
    A floating-gate-based synapse structure for neural computing fabricated by a standard double-polysilicon CMOS process is presented. Simulation and experimental results on conductance programmability and charge retention demonstrate the capability of this programmable synapse circuit. With this circuit a neural chip of 100K synapses complexity can be constructed using one megabit static-RAM fabrication technologies
  • Keywords
    CMOS integrated circuits; VLSI; neural nets; charge retention; conductance programmability; double-polysilicon CMOS process; floating-gate-based synapse structure; neural chip; neural computing; programmable synapse circuit; static-RAM fabrication technologies; Analog computers; CMOS process; Circuits and systems; Hardware; Multi-layer neural network; Neurons; Signal processing; Transconductance; Very large scale integration; Voltage;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-4094
  • Type

    jour

  • DOI
    10.1109/31.81862
  • Filename
    81862
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1292584