Title :
Analog floating-gate synapses for general-purpose VLSI neural computation
Author :
Lee, Bang W. ; Sheu, Bing J. ; Yang, Han
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
fDate :
6/1/1991 12:00:00 AM
Abstract :
A floating-gate-based synapse structure for neural computing fabricated by a standard double-polysilicon CMOS process is presented. Simulation and experimental results on conductance programmability and charge retention demonstrate the capability of this programmable synapse circuit. With this circuit a neural chip of 100K synapses complexity can be constructed using one megabit static-RAM fabrication technologies
Keywords :
CMOS integrated circuits; VLSI; neural nets; charge retention; conductance programmability; double-polysilicon CMOS process; floating-gate-based synapse structure; neural chip; neural computing; programmable synapse circuit; static-RAM fabrication technologies; Analog computers; CMOS process; Circuits and systems; Hardware; Multi-layer neural network; Neurons; Signal processing; Transconductance; Very large scale integration; Voltage;
Journal_Title :
Circuits and Systems, IEEE Transactions on
