Q-enhanced CMOS inductor using tapped-inductor feedback

A Q-enhanced inductor using the tapped-inductor feedback technique is presented. Compared with conventional transformer feedback architectures, this proposed technique not only compensates for resistive losses with low power consumption but also provides a high-inductance inductor. The semi-passive inductor, which consists of an NMOS transistor, a capacitor, and a tapped inductor has been designed, implemented and verified in a standard 0.18 m CMOS process. The measured resistance is about 1.0 at 3 GHz, and the 3.9 nH semi-passive inductor with a measured Q-peak of 74.2 around 3 GHz is also demonstrated. The semi-passive inductor draws 1.5 mA from a 0.8 V supply voltage while the chip size is 0.5 0.56 mm including all testing pads.