Title :
ECL fault modelling
Author :
Morandi, C. ; Niccolai, L. ; Fantini, F. ; Gaviraghi, S.
Author_Institution :
Dipartimento di Elettronica ed Automatica, Ancona Univ., Italy
fDate :
11/1/1988 12:00:00 AM
Abstract :
A procedure for describing an ECL circuit at the gate level is proposed. All voltages and currents which switch during circuit operation are described by logic variables, and thus the ´stuck line´ model can be effectively applied to describe circuit failures. Faults resulting from open connections and short circuits between transistor terminals are considered in detail.
Keywords :
digital integrated circuits; emitter-coupled logic; fault location; logic testing; ECL fault modelling; gate level; stuck line model;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings E
