Title :
Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions
Author :
Suzuki, Takeshi ; Higeta, Keiichi ; Fujimura, Yasuhiro ; Ando, Kazumasa ; Nambu, Hiroaki ; Yamagata, Ryo ; Hotta, Atsuo ; Yamaguchi, Kunihiko
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
A 1.5-ns-access 500-MHz synonym hit RAM has been developed using 0.25-/spl mu/m CMOS technology, which is the macro-cell to be used in microprocessor chips. We have proposed a virtual cache system with a synonym hit RAM, which achieves both high speed and large capacity because it solves the synonym problem that occurs with large-capacity cache systems. In this system, the RAM macro needs 576-bit parallel comparison and parity check functions. The configuration used achieves testability and low-power dissipation of large 576-bit data output. Moreover, the dynamic-NOR with a dynamic-inverter and sense-amplifier activation pulse generator are essential for reducing the comparison delay.
Keywords :
CMOS memory circuits; SRAM chips; cache storage; high-speed integrated circuits; low-power electronics; macros; 0.25 micron; 1.5 ns; 500 MHz; 576 bit; CMOS SRAM macro cell; dynamic NOR gate; dynamic inverter; low-power high-speed circuit; microprocessor chip; parallel comparison function; parity check function; sense-amplifier activation pulse generator; synonym hit RAM; synonym problem; testability; virtual cache system; CMOS technology; Clocks; Delay; Inverters; Microprocessor chips; Parity check codes; Power dissipation; Pulse generation; Random access memory; Testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
