Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients

Author

Rathod, S.S. ; Saxena, Alok Kumar ; Dasgupta, S.

Author_Institution

Dept. of Electron. & Comput. Eng., Indian Inst. of Technol., Roorkee, India

Volume

6

Issue

4

fYear

2012

fDate

7/1/2012 12:00:00 AM

Firstpage

218

Lastpage

226

Abstract

In this study, the authors evaluate different schemes of address decoders based on bulk, single gate (SG) silicon-on-insulator (SOI) and double gate (DG) FinFET technology. Schemes differ in terms of back gate connections, and swing on the enable and address lines. The analysis for delay, power dissipation and critical charge has been carried out. Radiation induced single event transients and multiple bit upsets in address decoder have been studied. For radiation hardened applications, tied gate configuration has been found to be good choice over bulk, SG-SOI and independent gate configurations. The effect of process parameter variations on different schemes has been studied. HSPICE simulations have been performed with 45 nm bulk, SG-SOI and DG-FinFET predictive technology models.

Keywords

MOSFET; SPICE; decoding; delays; radiation hardening (electronics); silicon-on-insulator; transients; DG FinFET technology; HSPICE simulations; SG-SOI; Si; back gate connections; delay; double-gate FinFET-based address decoder; independent gate configurations; multiple bit upsets; parameter variations; power dissipation; radiation induced single event transients; radiation-induced single-event-transients; single gate silicon-on-insulator; size 45 nm;

fLanguage

English

Journal_Title

Circuits, Devices & Systems, IET

Publisher

iet

ISSN

1751-858X

Type

jour

DOI

10.1049/iet-cds.2011.0253

Filename

6315721