A digital radio processor for channel demodulation and source decoding of satellite radio programs

New satellite based digital radio standards have been developed. The advantages of these standards (CD-like sound quality, small bandwidth requirements, embedded digital data services) require considerable larger modulation and demodulation efforts because forward error correction and sophisticated data compression techniques are used. The commercial success of these radio systems is closely related to the availability of low cost receiver equipment. This paper describes the concept and the architecture of a chipset that is designed for the demodulation of digital radio signals according to the European Astra digital radio (ADR) standard. The chipset consists of the multistandard sound processor (MSP) chip which is already widely used in standard satellite receivers or TV sets, and the newly developed digital radio processor (DRP) as a coprocessor for ADR decoding. The presented chipset allows a very cost-effective upgrade of standard satellite receivers for digital broadcast reception because substantial parts of the analog TV-sound processing are used for ADR-demodulation as well. Both ICs of the chipset are based on DSP-cores that provides a high flexibility with respect to modifications and additional features