Title :
New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over
Author :
Cho, Young In ; Chang, Nam Su ; Kim, Chang Han ; Park, Young-Ho ; Hong, Seokhie
Author_Institution :
Grad. Sch. of Inf. Manage. & Security, Korea Univ., Seoul, South Korea
Abstract :
Koç and Sunar proposed an architecture of the Mastrovito multiplier for the irreducible trinomial f(x)=xn+xk+1, where k ≠ n/2 to reduce the time complexity. Also, many multipliers based on the Karatsuba-Ofman algorithm (KOA) was proposed that sacrificed time efficiency for low space complexity. In this paper, a new multiplication formula which is a variant of KOA presented. We also provide a straightforward architecture of a non-pipelined bit-parallel multiplier using the new formula. The proposed multiplier has lower space complexity than and comparable time complexity to previous Mastrovito multipliers´ for all irreducible trinomials.
Keywords :
circuit complexity; multiplying circuits; polynomials; KOA; Karatsuba-Ofman algorithm; Mastrovito multiplier; irreducible trinomials; low space complexity; multiplication formula; nonpipelined bit-parallel multiplier; Complexity theory; Computer architecture; Delay; Logic gates; Polynomials; Bit-parallel multiplier; Mastrovito multiplication; finite field; irreducible trinomial; polynomial basis;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2011.2162594