Title :
Cost analysis: solder bumped flip chip versus wire bonding
Author_Institution :
Express Packaging Syst. Inc., Palo Alto, CA, USA
fDate :
1/1/2000 12:00:00 AM
Abstract :
The cost of wire bonding chips and solder bumped flip chips on boards or on organic substrates is studied. The effects of IC chip yields, gold and solder materials, and major equipment of these technologies on costs are examined. Useful equations and charts for determining the cost of and comparing the cost between these technologies are provided
Keywords :
flip-chip devices; integrated circuit economics; integrated circuit yield; lead bonding; reflow soldering; IC chip yields; cost analysis; organic substrates; solder bumped flip chip; solder materials; wire bonding; Assembly; Costs; Flip chip; Integrated circuit interconnections; Plastics; Semiconductor device packaging; Substrates; Testing; Wafer bonding; Wire;
Journal_Title :
Electronics Packaging Manufacturing, IEEE Transactions on
DOI :
10.1109/6104.827520
