DocumentCode :
1311422
Title :
Design Specification for BER Analysis Methods Using Built-In Jitter Measurements
Author :
Erb, Stefan ; Pribyl, Wolfgang
Author_Institution :
Inst. of Electron., Graz Univ. of Technol., Graz, Austria
Volume :
20
Issue :
10
fYear :
2012
Firstpage :
1804
Lastpage :
1817
Abstract :
Timing jitter is a major limiting factor for data throughput in serial high-speed interfaces, which forces an accurate analysis of the impact on system performance. Histogram-based methods have been developed for this purpose, and can directly relate collected jitter distributions with the bit-error rate (BER). However, real measurements suffer from limitations introduced by the hardware, such as limited sample size, a discrete number of bins or process variations. In this paper we investigate the performance of a widely used, powerful class of fitting methods, when used together with built-in jitter measurements (BIJM). We derive equations to specify minimum requirements for sample size and time resolution, and provide empirical relations to estimate the error statistics for typical test distributions. This allows designers to characterize key parameters of a BIJM design, and to find an optimum trade-off between hardware expense and system accuracy. A typical design example is also provided and validity of the empirical equations demonstrated with experimental jitter measurements. The equations can be used as tools for configuring a BIJM system, and to assist in realizing production tests and on-chip diagnostics.
Keywords :
error statistics; time measurement; timing jitter; BER analysis methods; BIJM system; bit-error rate analysis methods; built-in jitter measurements; collected jitter distributions; error statistics; fitting methods; histogram-based methods; on-chip diagnostics; sample size resolution; serial high-speed interfaces; test distributions; time resolution; timing jitter; Bit error rate; Jitter; Optimization; Phase locked loops; Bit-error rate (BER); Q-function; design specification; high-speed serial link; jitter analysis;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2011.2163325
Filename :
6006568
Link To Document :
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