Title :
Novel ternary JKL flip-flop
Author :
Zhuang, N. ; Wu, H.
Author_Institution :
Dept. of Electr. Eng., Hangzhou Univ., Zhejiang, China
fDate :
7/19/1990 12:00:00 AM
Abstract :
The logical design of ternary JKL edge-triggered flip-flop with triple-rail outputs is presented. The computer simulation and experimental circuit made with CMOS gates show that the flip-flop can realise the expected logic functions.
Keywords :
CMOS integrated circuits; flip-flops; ternary logic; CMOS gates; computer simulation; edge-triggered flip-flop; experimental circuit; ternary JKL flip-flop; triple-rail outputs;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19900741
