Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths

Author

Villacorta, Hector ; Hawkins, Chuck ; Champac, Victor ; Segura, Jaume ; Gomez, Roberto

Author_Institution

Nat. Inst. for Astrophys., Opt. & Electron. (INAOE), Puebla, Mexico

Volume

30

Issue

6

fYear

2013

fDate

Dec. 2013

Firstpage

70

Lastpage

79

Abstract

The number of open defects in vias has increased with the introduction of the copper process, smaller geometries, and via counts in the order of billions for modern integrated circuits. The authors investigate reliability risks by estimating the Median Time to Failure (MTF) as a function of the void size in vias placed. The number of open defects in vias has increased with the introduction of the copper process, smaller geometries, and via counts in the order of billions for modern integrated circuits. The authors investigate reliability risks by estimating the Median Time to Failure (MTF) as a function of the void size in vias placed on signal paths.

Keywords

copper; delay circuits; integrated circuit reliability; Cu; MTF; copper process; integrated circuits; median time to failure; open defects; reliability analysis; reliability risks; signal paths; small-delay defects; smaller geometries; via counts; via narrowing; void size; Current density; Electromigration; Failure analysis; Nanoscale devices; Reliability; Resistance; Blacks Law; Electromigration; Resistive Opens; Small Delay Defect; Via Duplication; Via Reliability;

fLanguage

English

Journal_Title

Design & Test, IEEE

Publisher

ieee

ISSN

2168-2356

Type

jour

DOI

10.1109/MDT.2013.2238578

Filename

6412849