DocumentCode :
1316983
Title :
NBTI model for analogue IC reliability simulation
Author :
Maricau, E. ; Gielen, G.
Author_Institution :
Dept. of Electr. Eng. ESAT-MICAS, ESAT-MICAS, Leuven, Belgium
Volume :
46
Issue :
18
fYear :
2010
fDate :
9/1/2010 12:00:00 AM
Firstpage :
1279
Lastpage :
1280
Abstract :
A complete and comprehensive physics-based model for negative bias temperature instability (NBTI) reliability simulation of analogue circuits in nanometre CMOS technologies is proposed. It includes typical NBTI peculiarities, such as relaxation after voltage stress reduction, and dependence on time-varying voltage stress, temperature and frequency. Including both the recoverable and the permanent NBTI component, the model offers a significant accuracy improvement over existing compact models. It is therefore well suited for accurate circuit reliability analysis and failure-time prediction. Additionally, the model includes only 10 process-dependent parameters, enabling easy calibration. The model was validated on a 1.4 EOT CMOS process.
Keywords :
CMOS analogue integrated circuits; integrated circuit reliability; 1.4 EOT CMOS process; NBTI model; analogue IC reliability simulation; circuit reliability analysis; comprehensive physics-based model; failure-time prediction; nanometre CMOS technology; negative bias temperature instability; time-varying voltage stress; voltage stress reduction;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el.2010.1971
Filename :
5567058
Link To Document :
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