DocumentCode :
1318258
Title :
IDDQ-VDD signature for CMOS circuits with bridging defects
Author :
Rodriguez-Montanes, R. ; Figueras, J.
Author_Institution :
Dept. d´´Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
Volume :
32
Issue :
24
fYear :
1996
fDate :
11/21/1996 12:00:00 AM
Firstpage :
2230
Lastpage :
2232
Abstract :
IDDQ-VDD signature differences between combinational and sequential CMOS circuits with bridging defects are presented. As VDD increases in combinational circuits with a bridging defect, the IDDQ of the defect subdomain increases monotonically as expected, and the rest of the circuit presents one or more local IDDQ maximums. In sequential circuits with bridging defects connecting control loop nodes the VDD-IDDQ signature presents intervals of a constant non-defective IDDQ value
Keywords :
logic testing; CMOS circuit; IDDQ-VDD signature; bridging defect; combinational circuit; sequential circuit;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19961530
Filename :
556783
Link To Document :
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