Synthesis of Bias-Scalable CMOS Analog Computational Circuits Using Margin Propagation

Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level performance. In our previous work, we had proposed margin propagation (MP) as an efficient piecewise linear (PWL) approximation technique to a log-sum-exp function and had demonstrated its advantages for implementing probabilistic decoders. In this paper, we present a systematic and a generalized approach for synthesizing analog piecewise-linear (PWL) computing circuits using the MP principle. MP circuits use only addition, subtraction and threshold operations and hence can be implemented using universal conservation principles like the Kirchoff´s current law. Thus, unlike the conventional translinear CMOS current-mode circuits, the operation of the MP circuits are functionally similar in weak, moderate, and strong inversion regimes of the MOS transistor making the design approach bias-scalable. This paper presents measured results from MP circuits prototyped in a 0.5 μm standard CMOS process verifying the bias-scalable property. As an example, we apply the synthesis approach towards designing linear classifiers and we verify its performance using measured results.