DocumentCode :
1324354
Title :
Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control
Author :
Ghaida, Rani S. ; Torres, George ; Gupta, Puneet
Author_Institution :
Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA
Volume :
24
Issue :
1
fYear :
2011
Firstpage :
93
Lastpage :
103
Abstract :
We propose shift-trim double-patterning lithography (ST-DPL), a cost-effective double-patterning technique for achieving pitch relaxation with a single photomask. The mask is re-used for the second exposure by applying a translational mask-shift. An additional non-critical trim exposure is applied to remove extra printed features. ST-DPL can be used to pattern critical layers and is very suitable for regular and gridded layouts, where redesign effort and area overhead are minimal. In this paper, the viability of ST-DPL is demonstrated through a design implementation at the poly and contacts layers in bidirectional layouts. Standard-cell layouts are constructed so as to avoid layout decomposition conflicts, which are found to be the limiting factor for the pitch relaxation that can be achieved with double patterning (ST-DPL as well as standard DPL). 2&times; pitch relaxation being associated with a considerable area overhead, 1.8 &times; pitch relaxation is achieved in our implementation while ensuring no layout decomposition conflicts and a small area overhead. Specifically, in comparison to layouts assumed to be feasible with a hypothetical single-patterning process, we observe virtually no area overhead when ST-DPL is applied to the poly layer (<; 0.3% cell-area overhead) and no more than 4.7% cell-area overhead when ST-DPL is applied at both the poly and contacts layers. The proposed method has many benefits over standard pitch-split double patterning: 1) cuts mask-cost to nearly half; 2) reduces overlay errors between the two patterns; 3) alleviates the bimodal line-width distribution problem in double patterning; and 4) slightly enhances the throughput of critical-layer scanners.
Keywords :
integrated circuit layout; integrated circuit manufacture; lithography; masks; area overhead; bidirectional layouts; bimodal line-width distribution; critical layers; improved overlay control; layout decomposition conflicts; limiting factor; non-critical trim exposure; pitch relaxation; shift-trim double-patterning lithography; single-mask double-patterning lithography; translational mask-shift; Layout; Libraries; Lithography; Logic gates; Manufacturing processes; Resists; Throughput; Bimodal CD distribution; double patterning; manufacturing throughput; mask cost; overlay; photomask; shift-trim; trim exposure;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2010.2076305
Filename :
5571032
Link To Document :
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