DocumentCode :
1325221
Title :
Throughput enhancement for repetitive internal cores in latency-insensitive systems
Author :
Zare, Mohsen ; Hessabi, Shaahin ; Goudarzi, Maziar
Author_Institution :
Dept. of Electron., Sci. & Res. Branch, Islamic Azad Univ., Tehran, Iran
Volume :
6
Issue :
5
fYear :
2012
fDate :
9/1/2012 12:00:00 AM
Firstpage :
342
Lastpage :
352
Abstract :
Latency-insensitive design (LID) is a correct by-construction methodology for system on chip design that prevents multiple iterations in synchronous system design. However, one problem in the LID is system throughput reduction. In this study, a protocol is proposed to increase the throughput of internal cores in the latency-insensitive systems when there are several repetitive structures. The validation of the protocol is checked for latency equivalency in various system graphs. A shell wrapper to implement the protocol is described and superimposed logic gates for the shell wrapper are formulated. Simulation is performed for 12 randomly generated systems and four actual systems. The simulation results represent protocol accuracy and show 57% throughput improvement on average compared with the scheduling-based methodology. The protocol also shows area reduction for the majority of simulated systems.
Keywords :
graphs; integrated circuit design; logic design; logic gates; protocols; scheduling; system-on-chip; LID; by-construction methodology; latency equivalency; latency-insensitive systems; multiple iterations; randomly generated systems; repetitive internal cores; scheduling-based methodology; shell wrapper; simulated systems; superimposed logic gates; synchronous system design; system on chip design; system throughput reduction; throughput enhancement; various system graphs;
fLanguage :
English
Journal_Title :
Computers & Digital Techniques, IET
Publisher :
iet
ISSN :
1751-8601
Type :
jour
DOI :
10.1049/iet-cdt.2011.0064
Filename :
6336877
Link To Document :
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