Phase jump technique for minimization of load voltage transients in SSSC-based voltage regulator

There is a large body of literature on modeling, design, and analysis of static-synchronous-series-compensator (SSSC) for voltage restoration and regulation. Most of them focus on investigating the impacts of source voltage disturbance only and give less emphasis on characterizing the whole system under load disturbances. This paper will derive a mathematical model to describe the static and dynamic characteristics of a capacitor-supported SSSC-based voltage regulator and will propose a phase jump technique that can minimize the load voltage fluctuation under load type and load value disturbances. The proposed technique has been applied to a 3kVA, 220V system. Experimental results show that the proposed technique can effectively reduce the load voltage fluctuation from 20% to 5% and reduce the settling time by 90% under a sudden change of the load type from inductive to capacitive, and vice versa.