Title :
Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers
Author :
Cabara, T.J. ; Fischer, Wilhelm C. ; Harrington, John ; Troutman, William W.
Author_Institution :
Bell Labs., Lucent Technol., Murray Hill, NJ, USA
fDate :
3/1/1997 12:00:00 AM
Abstract :
Several techniques to reduce the ground bounce effect in CMOS chips are described. The effective width of the predrive and final driver of a CMOS output buffer is automatically adjusted to compensate for process, voltage, and temperature (PVT) variations. The slew rate of the predrive nodes is controlled by introducing a digitally weighted capacitance. Finally, a compensated active resistance is inserted into both the power and ground leads to further dampen the oscillations. These techniques allow the buffer to behave uniformly over the entire PVT range. Measurements of a 0.5-μm CMOS test chip have demonstrated that these new buffers generate 2.5× less ground bounce when compared to conventional buffers. An external resistance is required to set a reference current
Keywords :
CMOS logic circuits; active networks; buffer circuits; capacitance; circuit oscillations; compensation; equivalent circuits; integrated circuit noise; integrated circuit packaging; 0.5 micron; 208-MQUAD package; CMOS chips; CMOS output buffers; compensated active resistance; damped LRC parasitic circuits; digitally weighted capacitance; ground bounce effect reduction; oscillations; simultaneously switched buffers; slew rate control; Automatic control; CMOS process; Capacitance; Driver circuits; Electrical resistance measurement; Land surface temperature; Semiconductor device measurement; Switching circuits; Testing; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of