Title :
A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrum transceiver IC [wireless LANs]
Author :
Wu, Jen-Shi ; Liou, Ming-Luen ; Ma, Hsi-Pin ; Chiueh, Tzi-Dar
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
10/1/1997 12:00:00 AM
Abstract :
In this paper, an all-digital differentially encoded quaternary phase shift keying (DEQPSK) direct sequence spread-spectrum (DSSS) transceiver is proposed. The transceiver consists of two parts: a baseband/IF spread-spectrum transmitter and a coherent intermediate frequency (IF) receiver. The center frequency of this IF receiver is 11 MHz and the sampling rate is 44 Msamples/s. Modulation/demodulation, carrier recovery, PN acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design were performed before layout implementation. The 0.8-μm N-well CMOS chip has a complexity of 56000 transistors with a core area of 3.5×3.5 mm2. Power dissipation is 92 and 145 mW at 2.6 and 3.3 V, respectively
Keywords :
CMOS digital integrated circuits; quadrature phase shift keying; spread spectrum communication; transceivers; wireless LAN; 0.8 micron; 145 mW; 2.6 V; 3.3 V; 44 MHz; 92 mW; N-well CMOS chip; PN acquisition; QPSK; baseband/IF spread-spectrum transmitter; carrier recovery; center frequency; coherent intermediate frequency receiver; core area; differential coding; differentially encoded quaternary phase shift keying; direct-sequence spread-spectrum transceiver; functional optimization; layout implementation; modulation/demodulation; power dissipation; sampling rate; transceiver IC; Baseband; Demodulation; Frequency; Modulation coding; Phase shift keying; Quadrature phase shift keying; Sampling methods; Spread spectrum communication; Transceivers; Transmitters;
Journal_Title :
Solid-State Circuits, IEEE Journal of
