A 0.5-V MTCMOS/SIMOX logic gate

Author

Douseki, Takakuni ; Shigematsu, Satoshi ; Yamada, Junzo ; Harada, Mitsuru ; Inokawa, Hiroshi ; Tsuchiya, Toshiaki

Author_Institution

NTT Syst. Electron. Lab., Kanagawa, Japan

Volume

32

Issue

10

fYear

1997

fDate

10/1/1997 12:00:00 AM

Firstpage

1604

Lastpage

1609

Abstract

This paper proposes a multithreshold CMOS (MTCMOS) circuit that uses SIMOX process technology. This MTCMOS/SIMOX circuit combines fully depleted low-threshold CMOS logic gates and partially depleted high-threshold power-switch transistors. The low-threshold CMOS gates have a large noise margin for fluctuations in operating temperature in addition to high-speed operation at the low supply voltage of 0.5 V. The high-threshold power-switch transistor in which the body is connected to the gate through the reverse-diode makes it possible to obtain large channel conductance in the active mode without any increase of the leakage current in the sleep mode. The effectiveness of the MTCMOS/SIMOX circuit is confirmed by an evaluation of a gate-chain test element group (TEG) and an experimental 0.5-V, 40-MHz, 16-b ALU, which were designed and fabricated with 0.25-μm MTCMOS/SIMOX technology

Keywords

CMOS logic circuits; SIMOX; logic gates; threshold logic; 0.25 micron; 0.5 V; 16 bit; 40 MHz; ALU; MTCMOS/SIMOX logic gate; SIMOX process technology; channel conductance; fully depleted low-threshold CMOS logic gate; gate-chain test element group; high-speed low-voltage operation; leakage current; multithreshold CMOS circuit; noise; partially depleted high-threshold power-switch transistor; temperature fluctuations; Active noise reduction; CMOS logic circuits; CMOS process; CMOS technology; Circuit noise; Circuit testing; Fluctuations; Logic gates; Low voltage; Temperature;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.634672

Filename

634672