Title :
A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 /spl mu/m SOI-CMOS technology
Author :
Nakura, Toru ; Ueda, Kimio ; Kubo, Kazuo ; Matsuda, Yoshio ; Mashiko, Koichiro ; Yoshihara, Tsutomu
Author_Institution :
Syst. LSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
5/1/2000 12:00:00 AM
Abstract :
This paper describes a 16:1 multiplexer using 0.18 /spl mu/m SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers.
Keywords :
CMOS digital integrated circuits; integrated circuit design; low-power electronics; multiplexing equipment; pipeline processing; silicon-on-insulator; very high speed integrated circuits; 0.18 micron; 2 V; 3.6 Gbit/s; 30 mW; 340 mW; I/O buffer design; SOI-CMOS technology; SONET; Si; low power operation; phase shift technique; pipelined multiplexer; selector architecture; telecommunication applications; ultra-high-speed operations; CMOS technology; Capacitance; Circuits; Data processing; Gallium arsenide; Large scale integration; Multiplexing; Paper technology; Pipelines; SONET;
Journal_Title :
Solid-State Circuits, IEEE Journal of
