Title :
A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors
Author :
Law, Chi Ho ; Hurst, Paul J. ; Lewis, Stephen H.
Abstract :
An 11-bit 160-MS/s four-channel time-interleaved double-sampled pipelined ADC implemented in a 0.35-μm CMOS process is described. Digital calibration is used to correct mismatch errors between channels as well as the memory errors that arise from the use of double sampling. The signal-to-noise-and-distortion ratio is improved from 45 to 62 dB after calibration with an 8.7-MHz input. The spurious-free dynamic range is increased from 47 dB to 79 dB.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; CMOS process; digital calibration; four channel time interleaved double sampled pipelined ADC; frequency 8.7 MHz; interchannel timing; memory errors; mismatch errors correction; signal-to-noise-and-distortion ratio; size 0.35 mum; spurious-free dynamic range; Calibration; Channel estimation; Delay; Detectors; Gain; Power dissipation; Analog-to-digital conversion; CMOS analog integrated circuits; digital background calibration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2010.2061630
