DocumentCode :
1333417
Title :
Low complexity architecture of bit parallel multipliers for GF(2m)
Author :
Shou, Guofa ; Mao, Zhi-Hong ; Hu, Ya ; Guo, Zhiyou ; Qian, Zhiming
Author_Institution :
Sch. of Inf. & Commun. Eng., Beijing Univ. of Posts & Telecommun., Beijing, China
Volume :
46
Issue :
19
fYear :
2010
Firstpage :
1326
Lastpage :
1327
Abstract :
A new architecture of multipliers for GF(2m) which accomplishes multiplication by lower-dimensional multiplication is proposed. The space complexity of the new multipliers is about 1/2 (1+1/r) of the ordinary ones, and it only needs two or three more XOR gate delays.
Keywords :
computational complexity; parallel algorithms; GF (2m); XOR gate delays; bit parallel multipliers; low complexity architecture; space complexity;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el.2010.1710
Filename :
5585041
Link To Document :
بازگشت