Implementation and Performance of DSP-Oriented Feedforward Power Amplifier Linearizer

In this paper, a digital signal processing-oriented implementation of feedforward power amplifier linearizer (DSP-FF) is introduced. In DSP-FF, the signal and error cancellation circuits are implemented, partially, in the DSP regime. By doing so, the number of bulky radio frequency (RF) components is reduced and their functionality is replaced by more flexible DSP circuitry and also various implementation nonidealities can be efficiently controlled. A two-stage estimation approach stemming from least-squares model fitting is proposed to identify proper DSP-FF coefficients. This improves the linearization performance by decoupling the effects of estimation inaccuracies between the two DSP-FF circuits. Furthermore, a comprehensive performance analysis of DSP-FF is carried out, taking also the memory of the core power amplifier into account. In particular, a closed-form expression for the intermodulation distortion reduction is derived in terms of the errors in the circuit coefficients. Also the measurement noise effects and large sample properties of the estimators are analyzed. The outcomes of computer simulated experiments verify the analytical results which are presented in this paper. Moreover, laboratory measurement setup utilizing a highly nonlinear RF power amplifier and contemporary telecommunication waveform demonstrates the linearization capability of the DSP-FF in terms of improvement in the measured adjacent channel leakage ratio.