DocumentCode
1335893
Title
Ultra-low voltage implicit multiplexed differential flip-flop with enhanced noise immunity
Author
Sung, W.-H. ; Lee, Ming-Chang ; Chung, Chen-Chen ; Lee, Chen-Yi
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
48
Issue
23
fYear
2012
Firstpage
1452
Lastpage
1454
Abstract
An ultra-low voltage 22T implicit multiplexed differential (IMD) flip-flop (FF) is proposed. An implicit multiplexer is designed to simplify the differential FF complexity, while its control data path is able to enhance the FF noise immunity as well. So, the fully static IMD-FF with modified differential topology provides a sufficient noise margin under voltage scaling. On the other hand, the IMD-FF operation avoids considerable DC current dissipation to save active power and suppresses the idle leakage by stacked transistors. The post-layout simulation in 90 nm CMOS process with 400 mV supply voltage shows that the IMD-FF achieves 56 active power and 42.2 leakage power reduction. The tolerable noise energy is enhanced by 18.9 on average. Finally, this work provides 93 function yield rate under the effect of process-voltage-temperature variations and 40 pJ input noise energy.
Keywords
CMOS integrated circuits; flip-flops; leakage currents; low-power electronics; 22T implicit multiplexed differential flip-flop; CMOS process; active power; differential FF complexity; enhanced noise immunity; idle leakage; leakage power reduction; leakage suppression; modified differential topology; noise margin; size 90 nm; stacked transistors; ultra-low voltage flip-flop; voltage 400 mV; voltage scaling;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el.2012.3016
Filename
6354223
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