Bit rate and protocol independent clock and data recovery

A design for a bit rate and protocol independent clock and data recovery circuit (CDRC) for use in optoelectronic regenerators is presented. A conventional phase-locked loop (PLL) has been extended to a combined phase/frequency-locked loop by adding two additional frequency detectors (FDs). This architecture guarantees reliable clock synchronisation of the input data with different line codes over a frequency range spanning multiple octaves