A Piecewise Linear 10 Bit DAC Architecture With Drain Current Modulation for Compact LCD Driver ICs

Author

Jeon, Yong-Joon ; Lee, Hyung-Min ; Lee, Sung-Woo ; Cho, Gyu-Hyeong ; Kim, Hyoung Rae ; Choi, Yoon-Kyung ; Lee, Myunghee

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon, South Korea

Volume

44

Issue

12

fYear

2009

Firstpage

3659

Lastpage

3675

Abstract

A piecewise linear 10 bit DAC for LCD data driver with robust interpolation method of drain current modulation is presented. It has higher effective bit resolution than the linear 10 bit switched-capacitor DAC when applied to nonlinear liquid crystal characteristics. By adopting a simultaneous design flow based on the estimations for the mismatch and nonlinearity effects on channel driver performance, the proposed DAC accomplishes good DNL of 0.37 LSB and excellent channel uniformity such that the mean and the standard deviation of the maximum output voltage deviations are 6.35 mV and 0.54 mV, respectively. The data driver with the new interpolation shows 8.2% shrinkage of chip area in comparison with the conventional 8 bit data driver with R-DAC.

Keywords

digital integrated circuits; digital-analogue conversion; driver circuits; compact LCD driver IC; drain current modulation; nonlinear liquid crystal characteristics; piecewise linear 10 bit DAC architecture; robust interpolation method; switched-capacitor digital to analog converters; voltage 0.54 mV; voltage 6.35 mV; Active matrix liquid crystal displays; Capacitors; Character generation; Driver circuits; Energy consumption; Interpolation; Liquid crystals; Piecewise linear techniques; Robustness; Voltage; Cascaded-dividing DAC; LCD; data driver; drain current modulation; interpolation; piecewise linear;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2009.2035547

Filename

5342341