Title :
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
Author :
Lee, Jri ; Wu, Ke-Chung
Author_Institution :
Electr. Eng. Dept., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase detector and automatic frequency locking technique is described. The phase detector achieves high-speed operation by mixing the clock with the data-transition pulses, providing output proportional to the phase error. The frequency acquisition loop utilizes the data phases rather than the clock phases to distill the frequency difference, and no external reference is used in this design. Fabricated in 90-nm CMOS technology, this circuit reveals rms and peak-to-peak jitter of 480 fs and 4.22 ps in response to a 231 -1 PRBS on the recovered clock while consuming 154 mW from a 1.5-V supply.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; frequency locked loops; high-speed techniques; mixers (circuits); phase detectors; CMOS technology; automatic frequency acquisition; automatic frequency locking technique; bit rate 20 Gbit/s; full-rate clock and data recovery circuit; high-speed operation; mixer-type linear phase detector; power 154 mW; size 90 nm; voltage 1.5 V; Automatic frequency control; CMOS technology; Circuits; Clocks; Error analysis; Frequency locked loops; Jitter; Phase detection; Phase frequency detector; Space vector pulse width modulation; Bit error rate (BER); clock and data recovery (CDR); frequency detector (FD); jitter generation; jitter tolerance; linear phase detector (PD);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2031042
