• DocumentCode
    134380
  • Title

    Multi-objective hardware-software co-optimization for the SNIPER multi-core simulator

  • Author

    Chis, Radu ; Vintan, Lucian

  • Author_Institution
    Comput. Sci. Dept., Tech. Univ., Cluj-Napoca, Romania
  • fYear
    2014
  • fDate
    4-6 Sept. 2014
  • Firstpage
    3
  • Lastpage
    9
  • Abstract
    Modern complex microarchitectures with multicore systems like CPUs, APUs (accelerated processing units) and GPUs require hundreds or thousands of hardware parameters to be fine-tuned to get the best results regarding different objectives like: performance, hardware complexity (integration area), power consumption, temperature, etc. These are only a few of the objectives needed to be taken into consideration when designing a new multicore system. Exploring this huge design space requires special tools like automatic design space exploration frameworks to optimize the hardware parameters. Although the microarchitecture might be very complex, the performance of the applications is also highly dependent on the degree of software optimization. This adds a new challenge to the DSE process. In this paper, using the multi-objective design space exploration tool FADSE, we tried to optimize the hardware and software parameters of the multicore SNIPER simulator running SPLASH-2 benchmarks suite. We optimized the hardware parameters (nr cores, cache sizes, cache associativity, etc.) and software parameters (GCC optimizations, threads, and scheduler) values that have been varied during the DSE process and shown the impact of these parameters on the optimization´s multi-objectives (performance, area and power consumption). Furthermore, for the best found Pareto configurations the temperatures will be computed so that in the end we will have a 4-dimensional objective space.
  • Keywords
    Pareto optimisation; computer architecture; graphics processing units; hardware-software codesign; multiprocessing systems; APU; CPU; FADSE; GPU; Pareto configuration; SNIPER multicore simulator; SPLASH-2 benchmark; accelerated processing units; automatic design space exploration; complex microarchitecture; multiobjective design space exploration tool; multiobjective hardware-software cooptimization; Hardware; Integrated circuit modeling; Multicore processing; Optimization; Software; Space exploration; Design Space Exploration; Multi-objective Optimization Algorithms; SPLASH-2 benchmarks; Sniper Multi-Core Simulator;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Intelligent Computer Communication and Processing (ICCP), 2014 IEEE International Conference on
  • Conference_Location
    Cluj Napoca
  • Print_ISBN
    978-1-4799-6568-7
  • Type

    conf

  • DOI
    10.1109/ICCP.2014.6936772
  • Filename
    6936772