Studies on reducing leakage current of large-area silicon microstrip sensors

8×4 cm² single-sided p⁺-i (or v)-n⁺ silicon microstrip sensors with coupling capacitors and polysilicon bias resistors were fabricated with the planar technology, and various techniques used to reduce the leakage currents of sensors and their results are presented. Different gettering processes have been employed to remove the impurities and defects from the sensor active regions, and the Electronic Research and Service Organization (ERSOs) Charge-Coupled Device (CCD) gettering technique, combined with backside polysilicon and oxide-nitride-oxide (ONO) deposition process, was found to be the most effective and suitable one. From the measurement results of the special p⁺-i (or v)-n⁺ junction test structures, it was found that the sensor leakage current mainly came from the side-wall leakage of its p⁺-strip. A modified LOCal Oxidation of Silicon (LOGOS) isolation process has been used to reduce this side-wall leakage. Also, the Sirtl-etch analysis of the sensor revealed that the side-wall leakage current has been caused by residual boron-implantation defects after annealing. These defects would concentrate along the edge of p⁺-strip and be enhanced to cause dislocations by the film-edge-induced stress effect. Several annealing techniques have also been studied to remove the boron-implantation damages. The fabricated prototype sensors have been tested in a beam at the CERN Super Proton Synchrotron area. The test results showed that the sensor concept under study is feasible