A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS

A PSK receiver (RX) is proposed that employs a digital-intensive architecture based on sub-sampling, Q-enhancement, and digital IF to enable low-power (1.3 mW) and low-voltage (0.6 V) operation. Implemented in 65 nm CMOS, this work is compatible with the IEEE 802.15.6 (WBAN) narrowband physical layer specification and achieves -91 dBm and -96 dBm sensitivity at 10^-3 BER for π/4-DQPSK and π/2-DBPSK modulation respectively. The proposed highly digital architecture and supply voltage scaling lead to a 3x improvement in RX energy efficiency and minimize silicon area consumption (~ 0.35 mm² in 65 nm CMOS) while achieving state-of-the-art sensitivity. While this implementation focuses on WBAN demodulation, the proposed architecture and circuit techniques are generally applicable to RX targeting ultra-low power consumption for sensor networks.