An analytical framework for area and switching power optimization of a fixed-point FFT algorithm

Predominantly all signal processing algorithms are developed with floating-point arithmetic. However for low power and real-time applications they are finally implemented on embedded systems with fixed-point arithmetic. Implementation of signal processing algorithm in fixed-point arithmetic involves a floating-point to fixed-point conversion process. Wordlength optimization plays a significant role in this conversion process, reducing area, power and latency while maintaining the accuracy constraint. Simulation and analytical approaches are two techniques used for optimizing the wordlengths. In simulation based approach a new fixed-point simulation is required to run for every modified wordlength. Bit true (fixed-point) simulations are not necessary to run for analytical based wordlength optimization methods. Therefore this approach requires the derivation of the cost model and the performance (signal to quantization noise ratio) as a function of wordlengths of different variables of the algorithm. Hence in this paper we have carried out a detailed study on the derivation of the cost model for fixed-point FFT algorithm. Cost models under various quantization modes are discussed and compared.