Title :
GaAs MESFET differential pass-transistor logic
Author :
Pasternak, John H. ; Salama, C. Andre T
Author_Institution :
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
fDate :
9/1/1991 12:00:00 AM
Abstract :
Two GaAs MESFET implementations of differential pass-transistor logic (DPTL) are presented. The DPTL logic technique combines the area efficiencies and high operation speeds of ratioless pass-transistor circuits with the additional features of noise immunity and low power dissipation. Circuit structures are presented for both depletion (D)-mode and enhancement/depletion (E/D)-mode MESFET technologies, and are compared with buffered FET logic (BFL) and direct-coupled FET logic (DCFL), respectively. Experimental results are provided to verify the functionality and the performance features of both DPTL forms
Keywords :
III-V semiconductors; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; integrated logic circuits; DPTL logic technique; GaAs; MESFET; depletion mode; differential pass-transistor logic; enhancement/depletion mode; low power dissipation; noise immunity; CMOS technology; Dynamic range; FETs; Gallium arsenide; Logic circuits; Logic devices; Logic functions; Logic gates; MESFET circuits; MOS devices;
Journal_Title :
Solid-State Circuits, IEEE Journal of
