Fault-Tolerant System Using 3-Value Logic Circuits

Author

Hu, Mou ; Mouftah, H.T.

Author_Institution

Department of Telecommunication and Computer Engineering; Shanghai Institute of Railway Technology; 1, Zhennan Lu, Shanghai 201803; P. R. CHINA.

Issue

2

fYear

1987

fDate

6/1/1987 12:00:00 AM

Firstpage

227

Lastpage

231

Abstract

A ternary decision circuit implemented in CMOS technology is proposed. It can be used in a duplex binary fault-tolerant system to replace both the matcher and the switch circuit. The resultant system is simpler than the conventional one. The reliable design of the ternary decision circuit is discussed in detail. A duplex 2-of-3-value fault-tolerant system can be formed by two 2-of-3-value processors and a TDC. This system is more powerful than a duplex binary system since it can provide automatic error correcting function for certain faults. All single faults can be divided into self-checked faults and secure faults. For any self-checked faults, the TDC is self-testing, strongly fault secure, and totally self-checking. For any secure faults, the TDC is strongly fault secure.

Keywords

CMOS logic circuits; Circuit faults; Fault tolerant systems; Logic circuits; Logic design; Logic functions; Multivalued logic; Signal processing; Switches; Switching circuits; 3-value logic; CMOS integrated circuit; Fault modeling; Fault tolerance; Self-checking circuit;

fLanguage

English

Journal_Title

Reliability, IEEE Transactions on

Publisher

ieee

ISSN

0018-9529

Type

jour

DOI

10.1109/TR.1987.5222349

Filename

5222349