Title :
Analysis of CMOS-compatible lateral insulated base transistors
Author :
Narayanan, E.M.S. ; Amaratunga, G. J A ; Milne, W.I. ; Humphrey, J.I. ; Huang, Q.
Author_Institution :
Dept. of Eng., Cambridge Univ., UK
fDate :
7/1/1991 12:00:00 AM
Abstract :
The authors describe the performance of various lateral insulated base transistors (LIBTs) fabricated with a 2.5-μm digital CMOS-compatible high-voltage integrated circuit (HVIC) process. Structural modifications have been proposed to the LIBTs reported to date, in order to improve their on-stage performance. The modifications have been achieved with the use of charge-controlled n+ buried layers incorporated within the device structures. These LIBTs are implemented with a novel HVIC process which is based on a 2.5-μm digital CMOS fabrication sequence. This process utilizes three additional steps carried out prior to the CMOS fabrication sequence. An important feature of this HVIC process is the use of a 400-Å gate oxide, which makes the power devices, fully compatible with the low-voltage digital circuits. During this work, a specific on-resistance of 0.016 Ω-cm2 and a turn-off delay of 90 ns have been obtained in an improved LIBT structure which is capable of withstanding up to 250 V
Keywords :
BIMOS integrated circuits; bipolar transistors; equivalent circuits; power integrated circuits; power transistors; semiconductor device models; 250 V; 90 ns; CMOS-compatible; HVIC fabrication process; LIBT structure; charge-controlled n+ buried layers; digital CMOS fabrication sequence; gate oxide; high-voltage integrated circuit; lateral insulated base transistors; low-voltage digital circuits; power devices; turn-off delay; Aerospace industry; CMOS process; Circuits; Costs; Insulated gate bipolar transistors; Insulation; MOSFETs; Microelectronics; Power electronics; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on