Title :
Sequential equivalence checking based on structural similarities
Author :
van Eijk, C.A.J.
Author_Institution :
Eindhoven Univ. of Technol., Netherlands
fDate :
7/1/2000 12:00:00 AM
Abstract :
Checking the functional equivalence of sequential circuits is an important practical problem. Because general algorithms for solving this problem require a state-space traversal of the product machine, they are computationally expensive. In this paper, we present a new method for sequential equivalence checking which utilizes functionally equivalent signals to prove the equivalence of both circuits, thereby avoiding the state-space traversal. The effectiveness of the proposed method is confirmed by experimental results on retimed and optimized ISCAS´89 benchmarks
Keywords :
circuit optimisation; finite state machines; formal verification; logic CAD; sequential circuits; timing; ISCAS´89 benchmarks; circuit optimization; functional equivalence; retiming; sequential circuits; sequential equivalence checking; structural similarities; Boolean functions; Circuit synthesis; Combinational circuits; Data structures; Formal verification; Integrated circuit synthesis; Logic; Optimization methods; Process design; Sequential circuits;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on