DocumentCode :
1360376
Title :
A Broadband Chip-Level Power-Bus Model Feasible for Power Integrity Chip-Package Codesign in High-Speed Memory Circuits
Author :
Chuang, Hao-Hsiang ; Hsu, Chih-Jung ; Hong, Jacky ; Yu, Chun-Huang ; Cheng, Argy ; Ku, Joseph ; Wu, Tzong-Lin
Author_Institution :
Dept. of Electr. of Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume :
52
Issue :
1
fYear :
2010
Firstpage :
235
Lastpage :
239
Abstract :
Based on two-port measurements, a distributed compact model and an extraction method for the power bus of a high-speed memory chip are proposed. The 1-D model is constructed according to the relative locations of the power and ground pads on the chip. The power bus around each power or ground pad is modeled by a section of resistor-inductor-capacitor (RLC) T-model, and the complete distributed model is formed by cascading all the T-model sections. The T-model at each section can be extracted through the measured two-port Z-parameters by using the Powell´s optimization method. Because the model is extracted from measured data, detailed (or proprietary) chip-layout information is not necessary. Another advantage is this compact model keeps the broadband accuracy by the distribution concept and is easy to link with the package model for the power integrity codesign.
Keywords :
DRAM chips; RLC circuits; chip scale packaging; electromagnetic compatibility; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit noise; optimisation; 1D model; DDR SDRAM chip; RLC T-model; Z-parameters; broadband chip level power bus model; distributed compact model; double data rate synchronous dynamic random access memory; electromagnetic compatibility; extraction method; ground pad; high speed memory circuits; integrated circuit noise; optimization method; power integrity chip-package codesign; resistor-inductor-capacitor T-model; two port measurement; Capacitors; Data mining; Network-on-a-chip; Optimization methods; Packaging; Power measurement; Power system modeling; Power systems; RLC circuits; SDRAM; Semiconductor device measurement; Ground bounce noise; power distribution network; power integrity (PI);
fLanguage :
English
Journal_Title :
Electromagnetic Compatibility, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9375
Type :
jour
DOI :
10.1109/TEMC.2009.2035614
Filename :
5356208
Link To Document :
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