Empirical Modeling and Extraction of Parasitic Resistance in Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors

We propose an extraction technique for parasitic resistance (RP) with L-, V_GS-, and V_DS-dependences even for large V_DS in amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs), by employing I_DS-V_GS characteristics (as a function of V_DS ) of two a-IGZO TFTs with different channel lengths ( L₁ and L₂ ). The resistance between the source and drain is modeled as an effective total resistance defined as RT^* ≡ V_DS/ID for all over the drain bias V_DS including both linear and saturation regions. The proposed method can be efficiently employed to model dc I-V characteristics and extract the parasitic resistance in a-IGZO TFTs even with short channel lengths, because the internal drain voltage (V_DS^´) is accurately calculated as a function of V_GS, V_DS, and L by deembedding the voltage drop across the parasitic resistance R_P.