Title :
A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management
Author :
Wang, Yih ; Bhattacharya, Uddalak ; Hamzaoglu, Fatih ; Kolar, Pramod ; Ng, Yong-Gee ; Wei, Liqiong ; Zhang, Ying ; Zhang, Kevin ; Bohr, Mark
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
This paper introduces a high-performance voltage-scalable SRAM design in a 32 nm strain-enhanced high-k + metal-gate logic CMOS technology. The 291 Mb SRAM design features a 0.171 ¿m2 six-transistor bitcell that supports a broad range of operating voltages for low-power and high-frequency embedded applications. The tileable 128 kb SRAM subarray achieves 72% array efficiency with 4.2 Mb/mm2 bit density, and consumes 5 mW of leakage power at the supply voltage of 1 V. The design provides 4 GHz and 2 GHz of operating frequencies at the supply voltages of 1.0 V and 0.8 V, respectively. The integrated power management scheme features close-loop memory array leakage control, floating bitline, and wordline driver sleep transistor, resulting in a 58% reduction in subarray leakage power consumption.
Keywords :
CMOS digital integrated circuits; SRAM chips; logic design; close-loop memory array leakage control; floating bitline; frequency 2 GHz; frequency 4 GHz; high-k + metal-gate logic CMOS technology; high-performance voltage-scalable SRAM design; integrated power management; size 32 nm; storage capacity 128 Kbit; storage capacity 291 Mbit; voltage 0.8 V; voltage 1 V; wordline driver sleep transistor; CMOS logic circuits; CMOS technology; Energy management; High K dielectric materials; High-K gate dielectrics; Logic design; Power supplies; Random access memory; Technology management; Voltage; 32 nm; CMOS memory integrated circuits; high-k + metal-gate; sleep transistor; static random-access memory (SRAM); variations;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2034082
