A workbench for computer architects

Author

Mitchell, Chad L. ; Flynn, Michael J.

Author_Institution

Comput. Syst. Lab., Stanford Univ., CA, USA

Volume

5

Issue

1

fYear

1988

Firstpage

19

Lastpage

29

Abstract

The authors present a high-level simulator that supports a top-down architectural analysis of embedded, custom applications. This tool characterizes more than 50 instruction-set variants and allows data such as instruction cached performance, data cache performance, register set size, and register allocation policy to be evaluated for all the architectures simultaneously. Designers also have more flexibility because they can trade off among high-level design constructs. Thus, they can evaluate relative performance before having to complete the machine specification at a lower level.<>

Keywords

CAD; buffer storage; computer architecture; performance evaluation; storage allocation; virtual machines; computer architecture simulation; data cache performance; high-level design constructs; high-level simulator; instruction cached performance; instruction-set variants; machine specification; register allocation policy; register set size; relative performance; top-down architectural analysis; workbench; Analytical models; Application software; Computational modeling; Computer architecture; Costs; Design engineering; Design optimization; Hardware; Registers; Software tools;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/54.668

Filename

668