Title :
A 65 nm CMOS 4-Element Sub-34 mW/Element 60 GHz Phased-Array Transceiver
Author :
Tabesh, Maryam ; Chen, Jiashu ; Marcu, Cristian ; Kong, Lingkai ; Kang, Shinwon ; Niknejad, Ali M. ; Alon, Elad
Author_Institution :
Univ. of California, Berkeley, Berkeley, CA, USA
Abstract :
This paper describes a low power and element-scalable 60 GHz 4-element phased array transceiver implemented in a standard 65 nm CMOS process. Using a 1.2 V supply, the array consumes <;34 mW/element including LO synthesis and distribution. Energy and area efficiency are achieved by utilizing a baseband phase shifting architecture, holistic impedance optimization, and lumped-element based design. Each receiver (RX) element provides 24 dB of gain with an average noise figure (NF) of 6.8 dB while the total saturated output power of the transmitter (TX) is 4.5 dBm. The array achieves 360° of phase shifting range with a worst-case measured phase resolution of 6 bits (TX)/ 5 bits (RX) while maintaining amplitude variations less than ±0.5 dB.
Keywords :
CMOS integrated circuits; electric impedance; energy conservation; optimisation; transceivers; CMOS 4-element subelement phased-array transceiver; LO synthesis; area efficiency; average noise figure; baseband phase shifting architecture; energy efficiency; frequency 60 GHz; impedance optimization; lumped-element based design; phase shifting range; power 34 mW; receiver element; size 65 nm; voltage 1.2 V; worst-case measured phase resolution; Beam steering; Noise measurement; Phase shift keying; Power amplifiers; Radio frequency; Transceivers; Transmitters; 60 GHz transceiver; Baseband phase shifting; CMOS; beam steering; energy efficient array; low noise amplifier (LNA); low power; millimeter wave integrated circuits; phase-locked loop (PLL); phased-array; power amplifier (PA);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2011.2166030