DocumentCode :
1364061
Title :
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery
Author :
Yin, Wenjing ; Inti, Rajesh ; Elshazly, Amr ; Talegaonkar, Mrunmay ; Young, Brian ; Hanumolu, Pavan Kumar
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
Volume :
46
Issue :
12
fYear :
2011
Firstpage :
3163
Lastpage :
3173
Abstract :
A digital clock and data recovery circuit (CDR) employs hybrid analog/digital phase detection to achieve linear loop dynamics and to eliminate the nonlinearity and quantization error of a bang-bang phase detector. The proposed architecture achieves constant jitter transfer bandwidth independent of input data jitter and reduces the sensitivity to digitally-controlled oscillator´s frequency quantization error and consecutive identical digits. The hybrid phase detection scheme also helps decouple jitter generation from jitter transfer characteristics of the CDR. The proto-type digital CDR fabricated in 0.13 μm CMOS technology achieves error-free operation (BER <; 10-12) for PRBS data sequences ranging from 27 - 1 to 231-1 sequence lengths over 0.5 Gb/s to 3.2 Gb/s data rates. At 2.5 Gb/s, the CDR consumes 7 mW power from a single 1.2 V supply and the recovered clock jitter is 5.7 ps rms.
Keywords :
CMOS digital integrated circuits; clock and data recovery circuits; jitter; oscillators; phase detectors; CMOS technology; PRBS data sequence; TDC; analog-digital phase detection; bang-bang phase detector; bit rate 0.5 Gbit/s to 3.2 Gbit/s; clock jitter transfer bandwidth; digital CDR circuit; digital clock and data recovery circuit; digitally-controlled oscillator frequency quantization error elimination; input data clock jitter; jitter generation decoupling; linear loop dynamic; nonlinearity elimination; offset-free data recovery; power 7 mW; size 0.13 mum; time 5.7 ps; voltage 1.2 V; Bandwidth allocation; Detectors; Jitter; Phase detection; Quantization; Voltage-controlled oscillators; Digital clock and data recovery circuit; hybrid analog/digital phase detection; jitter transfer bandwidth; linear loop dynamics;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2011.2168873
Filename :
6062657
Link To Document :
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