A fast variable-length decoder using plane separation

Author

Jeon, Jae Ho ; Park, Young Seo ; Park, Hyun Wook

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

Volume

10

Issue

5

fYear

2000

fDate

8/1/2000 12:00:00 AM

Firstpage

806

Lastpage

812

Abstract

This paper has developed a fast variable-length decoder which uses a plane separation technique to reduce the processing time of the feedback path in the decoder. The developed decoder performs two shift processes and a decision process concurrently. Therefore, the processing time in the feedback path of our developed variable length decoder can be improved and determined by the longest time among the three processes, not by the sum of their processing times together. Our simulation results show that the total processing time of our developed decoder makes about 30% improvement from that of the Sun and Lei´s (1991, 1992) decoder and their modified decoder when they are implemented with field programmable logic device

Keywords

decoding; feedback; field programmable gate arrays; parallel architectures; variable length codes; Huffman code; VLSI; bit parallel decoder; decision process; fast variable-length decoder; feedback path; field programmable logic device; high-speed entropy decoder; modified high-speed decoder; parallel PLA architecture; plane separation; processing time reduction; shift processes; simulation results; variable-length code; Bandwidth; Decoding; Entropy; Feedback; HDTV; Multimedia communication; Parallel processing; Programmable logic devices; Sun; Throughput;

fLanguage

English

Journal_Title

Circuits and Systems for Video Technology, IEEE Transactions on

Publisher

ieee

ISSN

1051-8215

Type

jour

DOI

10.1109/76.856458

Filename

856458