Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

Author

Mahatme, N.N. ; Jagannathan, S. ; Loveless, T.D. ; Massengill, L.W. ; Bhuva, B.L. ; Wen, S.-J. ; Wong, R.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA

Volume

58

Issue

6

fYear

2011

Firstpage

2719

Lastpage

2725

Abstract

It has been predicted that upsets due to Single-Event Transients (SETs) in logic circuits will increase significantly with higher operating frequency and technology scaling. For synchronous circuits manufactured at advanced technology nodes, errors due to single-event transients are expected to exceed those due to latch upsets. Experimental results presented in this paper quantify the contribution of logic errors to the total Soft-Error Rate (SER) for test circuits fabricated in a 40 nm bulk CMOS technology. These results can be used to develop guidelines to assist circuit designers adopt effective hardening strategies to reduce the SER, while meeting performance specifications for high speed logic circuits.

Keywords

CMOS logic circuits; flip-flops; radiation hardening; SER reduction; Soft-Error Rate; advanced technology nodes; bulk CMOS technology; circuit designers; combinational error rates; deep submicron process; hardening strategies; high speed logic circuits; latch upsets; logic errors; operating frequency; sequential error rates; single-event transients; size 40 nm; synchronous circuits; technology scaling; Combinational logic circuits; Error analysis; Logic circuits; Radiation hardening; Single event transient; Transient analysis; Combinational logic upsets; radiation hardening; single event transients (SETs); soft error rate (SER);

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2011.2171993

Filename

6068271