Title :
Heavy Ion Characterization and Monte Carlo Simulation on 32 nm CMOS Bulk Technology
Author :
Uznanski, Slawosz ; Gasiot, Gilles ; Roche, Philippe ; Autran, Jean-Luc ; Dugoujon, Laurent
Author_Institution :
Technol. R D, Central CAD & Design Solutions, Crolles, France
Abstract :
Heavy ion experimental test results carried out on static random-access memories (SRAMs) manufactured in bulk complementary metal-oxide semiconductor (CMOS) 32 nm are compared to Monte Carlo simulations. Additional simulation capabilities allow for insight in heavy ion cross-section variations as a function of temperature, power supply voltage, and process corners. Monte Carlo simulations of a radiation-hardened-by-design flip-flop based on a dual-interlocked storage cell latch have been performed and show similar sensitivities for 65 nm and 32 nm technologies. Finally, for the first time, the heavy-ion cross-section of the 20 nm bulk CMOS SRAMs is anticipated by simulation by using the latest available technology data.
Keywords :
CMOS integrated circuits; Monte Carlo methods; SRAM chips; flip-flops; integrated circuit modelling; ion beam effects; radiation hardening (electronics); CMOS bulk technology; Monte Carlo simulation; bulk CMOS SRAM; bulk complementary metal-oxide semiconductor; dual-interlocked storage cell latch; heavy ion characterization; heavy ion cross-section variations; heavy ion test; power supply voltage; process corners; radiation-hardened-by-design flip-flop; size 20 nm; size 32 nm; size 65 nm; static random-access memories; CMOS integrated circuits; CMOS technology; Flip-flops; Monte Carlo methods; SRAM chips; Semiconductor device modeling; Temperature measurement; Dual-interlocked storage cell (DICE); Monte–Carlo simulation; heavy ion SEU cross-section; radiation hardened by design (RHBD); static random-access memory (SRAM); tool suite for radiation reliability assessment (TIARA);
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2011.2170852
