Lithography-independent nanometer silicon MOSFETs on insulator

Future field-effect transistors should have control regions-also called channels or barriers-of a few tens of nanometers to achieve a transconductance of 1 Siemens per mm and beyond, f_T of 100 GHz and safe operating voltages beyond 1 V. This paper presents two approaches for the fabrication of such MOS transistors in silicon on insulator (SOI) on today´s average technology lines without resorting to nanometer lithography, but rather using differential doping available in reduced temperature epitaxy and implantation. With 6 nm oxinitride gate dielectrics, inner transconductances of 700 mS/mm at room temperature are reported